FPGA RISC-V CNN Accelerator

I need a RISC-V co-processor that plugs into my existing RISC-V core and dramatically speeds up convolutional layers in a CNN inference pipeline. The sole metric I care about is throughput: higher frames-per-second at the same clock. Power savings or memory tweaks are nice side effects, but raw speed is what will decide success.

Target platform is an FPGA prototype, so the RTL should be synthesis-ready and resource-aware. I am comfortable with Verilog, VHDL, SystemVerilog, as long as the code is clean and well-documented. AXI4 or an equally common on-chip bus is expected for host interaction, but I’m open to your suggestion if it fits the RISC-V ecosystem better.

Key points you should hit
• A custom instruction or tightly-coupled accelerator port on the RISC-V CPU for launching 2-D convolutions.
• Pipelined datapath able to keep the MAC array busy every cycle.
• Parameterisable kernel sizes and feature-map depths so I can explore trade-offs after synthesis.
• A simple software driver and reference C demo that calls the co-processor from bare-metal RISC-V code.
• Post-implementation report showing achieved MHz, LUTs, BRAMs, DSP usage, and the speed-up over a baseline software-only convolution. I will provide the baseline numbers.

Acceptance will be based on synthesising your design on my PYNQ-Z2 board and observing at least a 10× latency reduction on 3×3 kernels versus the unaccelerated code path.

If this scope feels clear and you have prior FPGA CNN experience, let’s talk and lock down milestones.