FPGA Digital Lock Guidance

I’m building a simple digital-lock proof-of-concept on a Nexys Artix-7 board using Vivado. At this stage the only feature I need is a basic lock-out mechanism—no fingerprint, keypad, or card reader yet. I already have a rough plan and can handle the introductory VHDL/Verilog myself, but I want an FPGA expert to:

• Review and refine my high-level design so the lock-out logic is clean and synthesizable.
• Supply or polish compact, well-commented code blocks where my initial draft falls short.
• Walk me through synthesis, implementation, and on-board testing in Vivado, stepping in to debug timing or constraint issues that pop up.

I’ll run the hardware on my end; you’ll provide guidance via chat or quick screenshares and, when necessary, share updated source files or constraint tweaks. The goal is a working, minimal lock-out system that reliably toggles a status LED and drives the on-board seven-segment display after successive failed attempts.

If you know the Nexys A7 toolchain inside out and enjoy mentoring while solving practical issues, I’d love your help.