Digital Calculator Architecture design

I need a complete architecture design that takes a digital calculator from concept to a specification ready for hardware description or PCB work. The immediate focus is the calculator itself—defining the data-path, control logic, memory mapping, and the way each core module cooperates to perform calculations accurately and efficiently. Once the high-level structure is solid I will extend the effort into detailed logic-gate diagrams and the encoding of every operation, so choices made now must scale.

Here is what the finished package should cover:
• Block-level architecture diagram that shows ALU, registers, control unit, I/O and clock domains.
• Signal-flow description (timing, control, data) clear enough to drop into VHDL / Verilog or a schematic capture tool.
• Instruction or operation encoding table that unambiguously links op-codes to control word bits.
• Written rationale for design decisions and resource estimates (gate count, memory, timing margins).
• Any simulation or verification artefacts that prove the arithmetic units behave correctly.

Submit a detailed project proposal when you respond—explain the approach, milestones, and any prior designs that prove you can take a calculator from high-level spec down to gate-level detail. Past work summaries are welcome, yet the proposal itself is what I will evaluate first.