Design 8-Bit FPGA CPU
Budget: $30 – $250 USD
Design a basic CPU (even 8‑bit or a minimal RISC‑V subset) in Verilog/VHDL,
implement it on a low‑cost FPGA board, and run a small instruction set or demo
program, emphasizing microarchitecture choices and timing closure.
Deliverables: HDL source, timing/area reports, simulation testbenches, and a brief
report on design methodology and verification strategy.
• HDL source files, well commented
• Simulation testbenches showing functional coverage of the instruction set
• Timing and area reports from synthesis/place-and-route
• A short, focused document describing micro-architecture choices, verification flow, and how timing closure was achieved
• Schematic/block diagram images that make the pipeline and datapath easy to follow
• A bitstream or programming file plus the demo program so I can replicate results quickly
Photos and short video
Schematics, and a short technical write‑up.
implement it on a low‑cost FPGA board, and run a small instruction set or demo
program, emphasizing microarchitecture choices and timing closure.
Deliverables: HDL source, timing/area reports, simulation testbenches, and a brief
report on design methodology and verification strategy.
• HDL source files, well commented
• Simulation testbenches showing functional coverage of the instruction set
• Timing and area reports from synthesis/place-and-route
• A short, focused document describing micro-architecture choices, verification flow, and how timing closure was achieved
• Schematic/block diagram images that make the pipeline and datapath easy to follow
• A bitstream or programming file plus the demo program so I can replicate results quickly
Photos and short video
Schematics, and a short technical write‑up.