Custom VHDL AXI Stream Core

I need a VHDL IP core that sits between two AXI4-Stream FIFOs, ingests a packet of N values, performs a simple arithmetic tweak, and pushes the result back out. Here is the exact scope:

• Interface: one AXI4-Stream slave for input, one AXI4-Stream master for output.
• Packet size: parameterised (e.g. default 8 words, 32-bit each).
• Operation: addition with a constant, hard-coded inside the source (no run-time configuration needed).
• Overflow handling: if more than N words arrive before TLAST, raise a dedicated error line and discard the surplus.
• Deliverables:
– Readable, synthesizable VHDL source for the core.
– A self-checking test-bench (ModelSim/Questa or similar) that drives typical and corner-case traffic, shows the error path, and logs results.
– Simple build notes so I can drop the files into Vivado or Quartus and recreate your simulation.

Signal naming and coding style should follow AXI4-Stream convention; please include generics for word width and packet length. Clear comments are expected so I can extend the design later.

If you’ve done AXI stream processing blocks before, this will feel familiar—let me see your proposed timeline and any similar work when you bid.