CNN Accelerator Design in Verilog

I need a Verilog implementation of a CNN accelerator with a DRAM interface. The accelerator should perform matrix multiplication on fixed-size matrices. The DRAM interface should be DDR3.

Key requirements:
- Functionality: Matrix multiplication only
- Matrix type: Fixed-size matrices
- DRAM interface: DDR3

Ideal skills and experience:
- Proficiency in Verilog
- Experience designing CNN accelerators
- Knowledge of DRAM interfaces, specifically DDR3
- Strong background in digital design and hardware description languages

Please provide relevant experience in your bids.