8-Bit SAR ADC VLSI Layout Design

The project is a VLSI CMOS circuit layout design for an 8-bit SAR ADC system. I already have the schematic design completed, and I need the physical transistor-level layout implementation based on that schematic. Details of the project: • Type of design: VLSI IC Layout / CMOS Layout • Project scope: Layout design of DFFSR and SAR-related blocks from the provided schematic • Reference materials: I already have the schematic and partial layout references • Software preferred: Cadence Virtuoso • Required work: * Transistor-level layout * DRC clean layout * LVS verification • Detail level required: Full custom layout suitable for academic project submission • Deliverables needed: * Layout files * DRC/LVS verified results