Alpha Datapath & Control Logic

I need a complete 32-bit datapath and the accompanying control logic that can execute the Alpha instruction subset consisting of sll, xor, and or. This is strictly a computer-architecture exercise, so the deliverable should remain at the logic-gate or block-diagram level rather than being written in an HDL.

What I expect to receive:
• A clearly drawn schematic (PDF or PNG) showing every functional block—register file, ALU, shifter, control unit, multiplexers, and any intermediate buses—wired for 32-bit operation.
• A micro-operation schedule or timing table that explains how each of the three instructions moves through the datapath.
• The control truth tables or finite-state-machine diagram that generate the required control signals.

I will test your work by walking through all three instructions and verifying signal values cycle by cycle, so please annotate the diagram or provide a brief walkthrough for each step. If you simulate the design in any tool, feel free to include screenshots or waveforms, but simulation files are optional. Clarity and correctness of the architectural design are the priority.