Building RISC V based SoC

Job ID: 38967629

Budget: $15 – $25 USD

I am in need of a RTL design and Verification expert using SystemVerilog and MATLAB to assist with my project.
Key tasks will involve:

- Work with me in building a RISC V SoC and do a Tapeout using Open source tools.
- Scripting to build UVM components from templates
- Automation using MATLAB, requiring a candidate with strong programming and automation skills.

The ideal candidate for this project will have expert-level experience with UVM, SystemVerilog and MATLAB You should have front end ASIC design experience, writing RTL and developing verification environment. Demonstrated proficiency in creating UVM test sequences and sequence items, as well as implementing coverage and assertions, will also be highly favorable. End goal is to build over few months a RISC V based Security IP. Understanding my project requirements, applying your expertise to solve the tasks at hand and delivering high-quality results are key to this project's success. Candidates will be selected based on a interview. Looking for someone interested to learn and develop in a team setting.
Please watch this video
https://www.youtube.com/watch?v=pYyv8BJ5n68
Related categories: Linux Verilog / VHDL MATLAB Digital ASIC Coding