DMA FPGA Firmware Development for PCIe Endpoint
Budget: $750 – $1,500 USD
We need an experienced FPGA engineer to implement a PCIe endpoint and custom DMA firmware on an Artix-7 class FPGA carrier. The end result must be a production-quality Vivado project and a working bitstream that cleanly enumerates on Windows 11 (Intel and AMD) and supports reliable bidirectional DMA for MRD and MWR flows. The candidate should be familiar with custom RTL DMA engines, PCIe TLP handling, MSI/MSI-X, and build automation in Vivado.
What we are asking for
Build a clean, reproducible Vivado project that targets an Artix-7 FPGA on a PCIe carrier. Preferred Vivado version is 2023.2; later versions acceptable if reproducible.
Deliver a working bitstream that programs the target board and enumerates in Windows 11 on Intel and AMD hosts without device-manager errors.
Implement a bidirectional DMA engine with clearly documented behavior and tunable parameters.
Provide full source, constraints, build scripts, and documentation so the client can rebuild the project from a clean checkout using non-GUI scripts.
Key technical expectations and tests you must support and document
Build and reproducibility
Provide TCL build scripts that generate and build the project end-to-end without GUI steps. Include a one-command wrapper to run the full flow.
State exact Vivado version and any environment setup. Provide a SHA-256 of the golden bitstream output.
Config space and enumeration behavior
Produce a config-space map that lists all capabilities and offsets, BAR sizes and types, which fields are writable, and any intentionally disabled features.
Provide a concise diff document showing how your implemented config-space structure maps to the supplied device dump structure (structural mapping, not device identity).
Interrupt model and tests
Implement MSI or MSI-X capability as required and document vector count, table offsets, and PBA semantics.
Deliver a short test script and logs that demonstrate writing vector entries, mask/unmask behavior, and correct delivery/quiescence of interrupts.
DMA engine and behavior
Implement a tunable MRD/MWR engine and document defaults and limits: MRRS/MPS, max outstanding reads, max TLP length, tag pool size, and ordering attributes.
Document error handling for UR, completion timeout, and partial completions; show how errors are reported back to the host.
Provide a small register interface or configuration region to change MRRS/MPS and outstanding tag counts at runtime if possible.
Reset, link training, and power handling
Demonstrate clean behavior across bus reset, device disable/enable from Device Manager, hot resets, and link retraining. Provide logs/screens showing re-enumeration without errors.
Throughput, stability, and soak tests
Provide a short stress run with mixed MRD and MWR traffic for 5 to 10 minutes, with logged counters for issued and completed TLPs and error counts. Acceptance requires no persistent device-manager errors and no OS instability.
Diagnostics and debug surface
Expose a minimal debug window or debug registers accessible from the host that include counters (issued reads, completed reads, issued writes, completed writes, last error code) and MSI mask state. Alternatively expose a UART or debug BAR for quick triage.
Documentation and deliverables
Bitstream file (.bin) that is immediately usable.
Full Vivado project folder including sources, .xdc constraints, block diagrams, IP settings, and TCL build scripts.
README with exact build instructions, required Vivado version, and steps to reproduce the bitstream.
Config-space map and register map for any control/debug registers you expose.
Test cookbook with exact commands and expected outputs for the acceptance tests.
Intel and AMD Windows 11 verification screenshots or logs that show Device Manager listing with no errors, and logs for MRD and MWR acceptance tests.
Third party code disclosure: list any external code or IP used and its license in a THIRD_PARTY file.
Licensing and IP
Deliverable must be reproducible and non-obfuscated. If licensed IP is required, list it and provide instructions for how the client can obtain required licenses. Upon full payment, ownership of delivered files transfers to the client for internal use.
Budget, timeline, and payment terms
Fixed budget: $1,250. Payment 50% upfront, 50% upon verified delivery and acceptance.
Timeline: 14 calendar days from project start.
Developer must provide at least two status updates during the 14 days. Unresponsiveness for more than 72 hours without notice may trigger refund eligibility.
* LEGAL *
We are a small group of passionate Cybersecurity professionals working on Anti Cheat technology for Indie Game developers.
Our projects use will be in closed lab environments and the projects will be used to strengthen detection methodology for DMA Anti Cheat bypassing.
No distribution of projects will be allowed for protection of gaming integrity.
What we are asking for
Build a clean, reproducible Vivado project that targets an Artix-7 FPGA on a PCIe carrier. Preferred Vivado version is 2023.2; later versions acceptable if reproducible.
Deliver a working bitstream that programs the target board and enumerates in Windows 11 on Intel and AMD hosts without device-manager errors.
Implement a bidirectional DMA engine with clearly documented behavior and tunable parameters.
Provide full source, constraints, build scripts, and documentation so the client can rebuild the project from a clean checkout using non-GUI scripts.
Key technical expectations and tests you must support and document
Build and reproducibility
Provide TCL build scripts that generate and build the project end-to-end without GUI steps. Include a one-command wrapper to run the full flow.
State exact Vivado version and any environment setup. Provide a SHA-256 of the golden bitstream output.
Config space and enumeration behavior
Produce a config-space map that lists all capabilities and offsets, BAR sizes and types, which fields are writable, and any intentionally disabled features.
Provide a concise diff document showing how your implemented config-space structure maps to the supplied device dump structure (structural mapping, not device identity).
Interrupt model and tests
Implement MSI or MSI-X capability as required and document vector count, table offsets, and PBA semantics.
Deliver a short test script and logs that demonstrate writing vector entries, mask/unmask behavior, and correct delivery/quiescence of interrupts.
DMA engine and behavior
Implement a tunable MRD/MWR engine and document defaults and limits: MRRS/MPS, max outstanding reads, max TLP length, tag pool size, and ordering attributes.
Document error handling for UR, completion timeout, and partial completions; show how errors are reported back to the host.
Provide a small register interface or configuration region to change MRRS/MPS and outstanding tag counts at runtime if possible.
Reset, link training, and power handling
Demonstrate clean behavior across bus reset, device disable/enable from Device Manager, hot resets, and link retraining. Provide logs/screens showing re-enumeration without errors.
Throughput, stability, and soak tests
Provide a short stress run with mixed MRD and MWR traffic for 5 to 10 minutes, with logged counters for issued and completed TLPs and error counts. Acceptance requires no persistent device-manager errors and no OS instability.
Diagnostics and debug surface
Expose a minimal debug window or debug registers accessible from the host that include counters (issued reads, completed reads, issued writes, completed writes, last error code) and MSI mask state. Alternatively expose a UART or debug BAR for quick triage.
Documentation and deliverables
Bitstream file (.bin) that is immediately usable.
Full Vivado project folder including sources, .xdc constraints, block diagrams, IP settings, and TCL build scripts.
README with exact build instructions, required Vivado version, and steps to reproduce the bitstream.
Config-space map and register map for any control/debug registers you expose.
Test cookbook with exact commands and expected outputs for the acceptance tests.
Intel and AMD Windows 11 verification screenshots or logs that show Device Manager listing with no errors, and logs for MRD and MWR acceptance tests.
Third party code disclosure: list any external code or IP used and its license in a THIRD_PARTY file.
Licensing and IP
Deliverable must be reproducible and non-obfuscated. If licensed IP is required, list it and provide instructions for how the client can obtain required licenses. Upon full payment, ownership of delivered files transfers to the client for internal use.
Budget, timeline, and payment terms
Fixed budget: $1,250. Payment 50% upfront, 50% upon verified delivery and acceptance.
Timeline: 14 calendar days from project start.
Developer must provide at least two status updates during the 14 days. Unresponsiveness for more than 72 hours without notice may trigger refund eligibility.
* LEGAL *
We are a small group of passionate Cybersecurity professionals working on Anti Cheat technology for Indie Game developers.
Our projects use will be in closed lab environments and the projects will be used to strengthen detection methodology for DMA Anti Cheat bypassing.
No distribution of projects will be allowed for protection of gaming integrity.