FSM diagram and circuit
Budget: $10 – $30 USD
Swimmy Fish
Project Description
Imagine that you are designing a game that requires a player to control a fish's depth under water. Pressing the spacebar causes it to move deeper in the water. If the player doesn't press the spacebar within a certain amount of time, then the fish moves up due to buoyancy. Let's divide the screen vertically into 4 regions: 0, 1, 2, 3, with 0 being the region closest to the water surface and 3 being the sea floor, as illustrated below. Pressing the spacebar corresponds to an input of 1, and the fish sinks to the next deeper region. Not pressing the spacebar corresponds to an input of 0 and the fish moves up to the next shallower region.
We can indicate the region where the fish is located using two bits: Outputs O1, O0. During Time 1 in the illustration below, bits O1 = 0 and O0 = 0 since the fish starts in region 0 closest to the water surface. Notice how these two region bits change in the last row of the illustration below as the fish rises and sinks due to the input in the second last row.
What happens if the fish swims above region 0? If the spacebar isn't pressed when the fish is already in region 0, it will stay in region 0 since it can't float any higher.
What happens if the fish swims below region 3? Let's change the level of the game! We can use another bit: Output O2 to represent transitioning to a new level in the game, starting back in region 0 and needing to swim down to region 3 again. We won't worry about tracking which game level we're on. Rather, we'll just output when a level change occurs using bit O2.
For the input sequence 1, 0, 0, 1, 1, 1, 0, 1, 1, 1, the game outputs the sequence as shown in the last row of this illustration:
p1image.png
FSM Description
This simple game can be implemented as a finite state machine (FSM). For this project, you need to design the combinational and sequential logic circuit that implements this FSM.
INPUT: In
In = 1 increments the state. However, if the state is 3 then wrap around to state 0 and indicate a level change.
In = 0 decrements the state. However, if the state is 0 then remain in state 0.
OUTPUTS: O2, O1, O0
O1, O0 represent the current state in binary, where O0 is the least significant bit and O1 is the most significant bit. For example, when the current region is 1, the FSM should output O1 = 0 and O0 = 1.
O2 represents the level change. It is 1 only when the current state is 3 and the input is 1.
Requirements
First, get a copy of this template fileDownload template file, which you're required to fill in to complete your design. It helps you structure your work and it helps us with grading.
Do the parts of your design in this order:
PART 1: Design the state diagram for the FSM described above. Outputs (O2, O1, O0) do not need to be indicated in part 1.
PART 2: Fill in the truth table to correspond with the logic specified above.
PART 3: Draw the logic circuit that implements the design.
Make sure to put a clear dot on all connections of 3 or more incoming lines.
Note that the circuit template might have extra components that aren't needed for the design.
If you know how to simplify logic from another class, DO NOT simplify this problem.
The concepts for this project are covered during week 5, which includes discussing the similar example in section 3.6.4 in the textbook.
Project Description
Imagine that you are designing a game that requires a player to control a fish's depth under water. Pressing the spacebar causes it to move deeper in the water. If the player doesn't press the spacebar within a certain amount of time, then the fish moves up due to buoyancy. Let's divide the screen vertically into 4 regions: 0, 1, 2, 3, with 0 being the region closest to the water surface and 3 being the sea floor, as illustrated below. Pressing the spacebar corresponds to an input of 1, and the fish sinks to the next deeper region. Not pressing the spacebar corresponds to an input of 0 and the fish moves up to the next shallower region.
We can indicate the region where the fish is located using two bits: Outputs O1, O0. During Time 1 in the illustration below, bits O1 = 0 and O0 = 0 since the fish starts in region 0 closest to the water surface. Notice how these two region bits change in the last row of the illustration below as the fish rises and sinks due to the input in the second last row.
What happens if the fish swims above region 0? If the spacebar isn't pressed when the fish is already in region 0, it will stay in region 0 since it can't float any higher.
What happens if the fish swims below region 3? Let's change the level of the game! We can use another bit: Output O2 to represent transitioning to a new level in the game, starting back in region 0 and needing to swim down to region 3 again. We won't worry about tracking which game level we're on. Rather, we'll just output when a level change occurs using bit O2.
For the input sequence 1, 0, 0, 1, 1, 1, 0, 1, 1, 1, the game outputs the sequence as shown in the last row of this illustration:
p1image.png
FSM Description
This simple game can be implemented as a finite state machine (FSM). For this project, you need to design the combinational and sequential logic circuit that implements this FSM.
INPUT: In
In = 1 increments the state. However, if the state is 3 then wrap around to state 0 and indicate a level change.
In = 0 decrements the state. However, if the state is 0 then remain in state 0.
OUTPUTS: O2, O1, O0
O1, O0 represent the current state in binary, where O0 is the least significant bit and O1 is the most significant bit. For example, when the current region is 1, the FSM should output O1 = 0 and O0 = 1.
O2 represents the level change. It is 1 only when the current state is 3 and the input is 1.
Requirements
First, get a copy of this template fileDownload template file, which you're required to fill in to complete your design. It helps you structure your work and it helps us with grading.
Do the parts of your design in this order:
PART 1: Design the state diagram for the FSM described above. Outputs (O2, O1, O0) do not need to be indicated in part 1.
PART 2: Fill in the truth table to correspond with the logic specified above.
PART 3: Draw the logic circuit that implements the design.
Make sure to put a clear dot on all connections of 3 or more incoming lines.
Note that the circuit template might have extra components that aren't needed for the design.
If you know how to simplify logic from another class, DO NOT simplify this problem.
The concepts for this project are covered during week 5, which includes discussing the similar example in section 3.6.4 in the textbook.