Simulating a processor scheduler based on contiguous memory allocation

The purpose of this assignment is to implement a simulation system that simulates the activity of an FCFS processor scheduler based on a contiguous memory allocation approach. It is assumed that the system contains an infinity number of processors and finite amount of memory to host the processors' address spaces. Thus, any process can be put running when it arrives to the system as long as enough memory to host its address space is available. Otherwise, it is put in a swap area while waiting for the availability of memory. Every process is considered to be composed of a single CPU burst, whose lifetime in memory is known in advance.

The following terms are key for a good understanding of the system:

pid - process indentification, a positive, greater than zero integer value that uniquely identifies a process;
arrival time - the time at which a process arrives to the system;

lifetime in memory - the interval of time a process must stay in main memory in order to complete its execution;

activation time - the time at which a process' address space is put in main memory;

finish time - the time at which a process completes its execution, and so the memory it uses can be released;

address space profile - the number of segments the address space of a process comprises and their sizes;

block of memory - a contiguous area in main memory;

address space mapping - the set of blocks in main memory used to host the address space of a process;

process state - the state at which a process is at a given moment in time, being one of NEW, ACTIVE, SWAPPED, FINISHED, or DISCARDED


The system is composed of several main modules:

pct, which holds information about the processes being simulated, after their arrival to the system

mem, which deals with the allocation / deallocation of memory used by processes

feq, which deals with the future events that command the simulation

swp, which holds information about the swapped processes

sim, which provides means to make and control the simulation

There is also a number of auxiliary modules:

probing, which provides a probing mechanism
binselection, which allows to a binary version of a function
exception, which provides a way to throw exceptions

The simulation is driven by an input file which defines the arrival time of a list of processes, along with their time of execution and memory needs for their address spaces. The simulation must show how the scheduling takes place and where in memory were the address spaces stored.

Only modules pct, feq, mem, swp and sim are to be developed in this assignment.

The information about this project will be given up front.