Cortex M3
Budget: $10 – $30 CAD
A number of instructions can be both 16-bit as well as 32-bit depending upon the circumstance.
Write an example where the instruction is forced to 16-bit and another example where it is forced to
32-bit. What general purpose registers are most 16-bit instructions restricted to?
2. Why might an assembler decide to use a 16-bit instruction to implement your C code instead of a
32-bit instruction?
3. The details for each instruction in the Cortex-M3 are covered in the Generic User Guide:
https://developer.arm.com/documentation/dui0552/latest/
3.4.3 Contains the details for Load and Store with register offset. In the example:
LDRSB R0, [R5, R1, LSL #1]
What does SB do? If we have 0x53 and 0xF4 in memory and we load them individually into
R0 with LDRSB, what is R0 for each respectively?
Hint: you can always use the debugger to figure it out using this code:
ALIGN
BYTE_1 DCB 0xF4
BYTE_2 DCB 0x53
LDR R1, =BYTE_1
LDRSB R0, [R1]
LDR R1, =BYTE_2
LDRSB R0, [R1]
Write an example where the instruction is forced to 16-bit and another example where it is forced to
32-bit. What general purpose registers are most 16-bit instructions restricted to?
2. Why might an assembler decide to use a 16-bit instruction to implement your C code instead of a
32-bit instruction?
3. The details for each instruction in the Cortex-M3 are covered in the Generic User Guide:
https://developer.arm.com/documentation/dui0552/latest/
3.4.3 Contains the details for Load and Store with register offset. In the example:
LDRSB R0, [R5, R1, LSL #1]
What does SB do? If we have 0x53 and 0xF4 in memory and we load them individually into
R0 with LDRSB, what is R0 for each respectively?
Hint: you can always use the debugger to figure it out using this code:
ALIGN
BYTE_1 DCB 0xF4
BYTE_2 DCB 0x53
LDR R1, =BYTE_1
LDRSB R0, [R1]
LDR R1, =BYTE_2
LDRSB R0, [R1]