RISC-V CPU Custom Creation: Chisel Knowledge Required
Budget: $30 – $250 USD
We are seeking a skilled hardware developer for a project involving the development of a RISC-V CPU using the Chisel hardware construction language. The project is based on the Davis IN-Order CPU (DINO CPU) design, closely aligned with the model in Patterson and Hennessey's 'Computer Organization and Design.' The developer will be responsible for integrating provided CPU components and templates into a functioning processor, using Chisel to describe the hardware implementation.
Key Responsibilities:
Understand and utilize Chisel, a Scala-based hardware description language, to develop the CPU.
Integrate pre-written CPU components following provided interfaces.
Debug, test, and refine the CPU design to ensure proper functionality.
Collaborate with the team for integrating the CPU into a larger system.
Skills Required:
Proficiency in Chisel and Scala.
Strong background in CPU architecture and hardware design.
Experience with RISC-V CPU design and the Verilog hardware description language.
Familiarity with Docker and GitHub Codespaces for development environment setup.
Ability to read and interpret hardware design specifications and documentation."
Key Responsibilities:
Understand and utilize Chisel, a Scala-based hardware description language, to develop the CPU.
Integrate pre-written CPU components following provided interfaces.
Debug, test, and refine the CPU design to ensure proper functionality.
Collaborate with the team for integrating the CPU into a larger system.
Skills Required:
Proficiency in Chisel and Scala.
Strong background in CPU architecture and hardware design.
Experience with RISC-V CPU design and the Verilog hardware description language.
Familiarity with Docker and GitHub Codespaces for development environment setup.
Ability to read and interpret hardware design specifications and documentation."