Teensy 4.1 One-Cycle FSK

Job ID: 39994159

Budget: €30 – €250 EUR

I’m building a proof-of-concept transmitter that must output a single, precisely timed cycle of FSK per data bit on a Teensy 4.1. The bit stream is stored exactly as
volatile uint8_t dataBits[] = {1,0,1,1,0,0,1};
and each symbol maps to one full cycle:
• 0 → 70.8 kHz
• 1 → 73.2 kHz

Everything must lock to an external clock connected to the Teensy; accuracy is paramount, so please squeeze as much timing precision as the hardware allows.

What I need from you
• A complete schematic and circuit design that shows all Teensy pins, clock interface, any buffering or filtering you deem necessary, and test-point recommendations.
• Fully functional Arduino-style code for the Teensy 4.1 that reads the array, gates exactly one cycle at the correct frequency for each bit, then advances to the next symbol. Basic in-line comments are enough—I’m comfortable reading concise, purposeful code.
• You will source all additional requirements yourself (components, libraries, reference material); I’m supplying no extra resources beyond the description above.

I’ll verify the work with an oscilloscope and a frequency counter, so the generated cycles must land cleanly on the two target frequencies without drift or phase glitches. When those measurements look good, the project is complete.