Sky130 CMOS Inverter Full Flow
Budget: $750 – $1,500 USD
Abstract: Manufacturing-Ready 130nm CMOS Inverter Design
The objective of this project is to design, verify, and prepare a standard CMOS inverter for fabrication using the SkyWater 130nm Open-Source PDK. Unlike theoretical projects, this work follows a complete "Silicon-to-GDS" flow. The process begins with Schematic Capture and Pre-Layout Simulation to establish electrical baselines. This is followed by Physical Layout, where the geometric structures of the NMOS and PMOS transistors are manually drawn according to strict foundry Design Rule Checks (DRC). The design is then validated through Layout vs. Schematic (LVS) to ensure physical-electrical equivalence. Finally, Parasitic Extraction (PEX) is performed for Post-Layout Simulation to account for real-world wire resistance and capacitance, culminating in the generation of a GDSII stream file for tape-out readiness.
The Step-by-Step Procedure expectation:
Step 1: Schematic and Testbench Setup
* The Action: "Start by drawing the inverter circuit in Xschem using Sky130 primitive components."
* The Goal: To define the transistor sizes (Width/Length) and run a DC sweep to see the Voltage Transfer Curve (VTC).
Step 2: Pre-Layout Simulation
* The Action: "Use Ngspice to simulate the 'ideal' circuit."
* The Goal: To measure the switching threshold (V_M) and basic propagation delay without any wire interference.
Step 3: Physical Layout (The "Manufacturing" Part)
* The Action: "Use Magic VLSI to draw the physical layers—N-well, P-diffusion, Polysilicon, and Metal-1."
* The Goal: To create the actual physical footprint of the inverter. Must ensure it is DRC Clean, meaning it follows all the foundry's safety rules for manufacturing.
Step 4: Verification (LVS)
* The Action: "Run Netgen to perform Layout vs. Schematic (LVS) verification."
* The Goal: To prove that the physical drawing (Step 3) perfectly matches my electrical diagram (Step 1). If they don't match, the chip won't work.
Step 5: Post-Layout Extraction and GDSII
* The Action: "Extract the 'parasitics' (hidden resistance and capacitance) from the layout and re-simulate the circuit."
* The Goal: To show the true performance of the chip. Finally, export the GDSII file, which is the final binary file the factory uses to print the silicon.
Summary of Requirements
1. Technology: SkyWater 130nm (sky130A).
2. Tools: Xschem (Schematic), Magic (Layout), Netgen (LVS), Ngspice (Simulation).
3. Required/ Expected Handoffs : .spice (Schematic), .mag (Layout), .gds (Manufacturing file), and a comparison report of Pre-layout vs. Post-layout delay and a complete academic project report including all the details.
NOTE: **I need to give a demo of this project. So, everything must also be installed on my laptop/PC and also you will have to explain me the process and how to answer any questions which might be asked during the demo.**
Acceptance
Everything should open without errors in the stated open-source tools, LVS must be clean, and the timing comparison must be clearly tabulated in the report. Deliverables should be zipped and ready for download along with installation of tools and explanation of the workflow so I can demonstrate the full flow during my presentation.
The objective of this project is to design, verify, and prepare a standard CMOS inverter for fabrication using the SkyWater 130nm Open-Source PDK. Unlike theoretical projects, this work follows a complete "Silicon-to-GDS" flow. The process begins with Schematic Capture and Pre-Layout Simulation to establish electrical baselines. This is followed by Physical Layout, where the geometric structures of the NMOS and PMOS transistors are manually drawn according to strict foundry Design Rule Checks (DRC). The design is then validated through Layout vs. Schematic (LVS) to ensure physical-electrical equivalence. Finally, Parasitic Extraction (PEX) is performed for Post-Layout Simulation to account for real-world wire resistance and capacitance, culminating in the generation of a GDSII stream file for tape-out readiness.
The Step-by-Step Procedure expectation:
Step 1: Schematic and Testbench Setup
* The Action: "Start by drawing the inverter circuit in Xschem using Sky130 primitive components."
* The Goal: To define the transistor sizes (Width/Length) and run a DC sweep to see the Voltage Transfer Curve (VTC).
Step 2: Pre-Layout Simulation
* The Action: "Use Ngspice to simulate the 'ideal' circuit."
* The Goal: To measure the switching threshold (V_M) and basic propagation delay without any wire interference.
Step 3: Physical Layout (The "Manufacturing" Part)
* The Action: "Use Magic VLSI to draw the physical layers—N-well, P-diffusion, Polysilicon, and Metal-1."
* The Goal: To create the actual physical footprint of the inverter. Must ensure it is DRC Clean, meaning it follows all the foundry's safety rules for manufacturing.
Step 4: Verification (LVS)
* The Action: "Run Netgen to perform Layout vs. Schematic (LVS) verification."
* The Goal: To prove that the physical drawing (Step 3) perfectly matches my electrical diagram (Step 1). If they don't match, the chip won't work.
Step 5: Post-Layout Extraction and GDSII
* The Action: "Extract the 'parasitics' (hidden resistance and capacitance) from the layout and re-simulate the circuit."
* The Goal: To show the true performance of the chip. Finally, export the GDSII file, which is the final binary file the factory uses to print the silicon.
Summary of Requirements
1. Technology: SkyWater 130nm (sky130A).
2. Tools: Xschem (Schematic), Magic (Layout), Netgen (LVS), Ngspice (Simulation).
3. Required/ Expected Handoffs : .spice (Schematic), .mag (Layout), .gds (Manufacturing file), and a comparison report of Pre-layout vs. Post-layout delay and a complete academic project report including all the details.
NOTE: **I need to give a demo of this project. So, everything must also be installed on my laptop/PC and also you will have to explain me the process and how to answer any questions which might be asked during the demo.**
Acceptance
Everything should open without errors in the stated open-source tools, LVS must be clean, and the timing comparison must be clearly tabulated in the report. Deliverables should be zipped and ready for download along with installation of tools and explanation of the workflow so I can demonstrate the full flow during my presentation.