STM32 Nucleo Input Board Design
Budget: $15 – $25 USD
I need a plug-on input board for an STM32 Nucleo that cleanly brings five external signals and one digital contact into the MCU. All work must be done in KiCad, and I will require both the finished schematic and the routed PCB files.
Signals to condition
• 0–100 V DC to A0
• 0–50 mV DC to A1
• 0–50 mV DC to A2
• −5 V…+5 V DC to A3, with the same node also allowing 0–100 V AC sensing (A4)
• Digital input (NO/NC selectable) to D4
Electrical constraints
The board will be powered from 9 – 36 V DC. Please include regulation that provides the rails required by the Nucleo (typically 5 V and 3.3 V) as well as any local analog references, with basic reverse-polarity and surge protection.
Interface requirements
Expose TX and RX from the Nucleo’s USART as an RS-485 half-duplex transceiver on a pluggable terminal.
Deliverables
• KiCad schematic with all component libraries
• KiCad PCB layout (ready for a two-layer fab run unless you justify more)
• Gerber and drill files, pick-and-place, and an annotated BOM
• Brief design note describing the input scaling, protection choices, and power-tree calculations
I will review the files in KiCad, verify that each input range reaches the MCU within 0–3.3 V, and spot-check the BOM before approving. Let me know early if any range needs special handling so we can agree on the approach.
Signals to condition
• 0–100 V DC to A0
• 0–50 mV DC to A1
• 0–50 mV DC to A2
• −5 V…+5 V DC to A3, with the same node also allowing 0–100 V AC sensing (A4)
• Digital input (NO/NC selectable) to D4
Electrical constraints
The board will be powered from 9 – 36 V DC. Please include regulation that provides the rails required by the Nucleo (typically 5 V and 3.3 V) as well as any local analog references, with basic reverse-polarity and surge protection.
Interface requirements
Expose TX and RX from the Nucleo’s USART as an RS-485 half-duplex transceiver on a pluggable terminal.
Deliverables
• KiCad schematic with all component libraries
• KiCad PCB layout (ready for a two-layer fab run unless you justify more)
• Gerber and drill files, pick-and-place, and an annotated BOM
• Brief design note describing the input scaling, protection choices, and power-tree calculations
I will review the files in KiCad, verify that each input range reaches the MCU within 0–3.3 V, and spot-check the BOM before approving. Let me know early if any range needs special handling so we can agree on the approach.