Optimize MBE Multiplier Cadence

I am refining an existing Modified Booth Encoder (MBE) multiplier taken from the attached IEEE paper and need your expertise in Cadence Virtuoso (90 nm CMOS). The top priority is lowering the overall Power-Delay Product; gains in raw power, speed, or area are welcome, but PDP is the principal success metric.

What you will do
• Build a full-custom, transistor-level schematic of the improved MBE multiplier in Cadence Virtuoso, staying within the same 90 nm node used in the reference paper.
• Run exhaustive Spectre simulations to characterise average and peak power, worst-case delay, total area, transistor count, and the resulting PDP.
• Compare every metric against the baseline figures I will extract from the IEEE reference; clear percentage improvements must be shown.
• Analyse the circuit choices that led to the gains, positioning the work so it can be defended in an IEEE/Springer-style publication.

Deliverables
• Cadence schematic files and netlists.
• Complete simulation decks and waveforms (raw data + annotated plots).
• A comparison table outlining power, delay, area, transistor count and PDP for both baseline and your design.
• A concise research-oriented report (≈6–8 pages) formatted for IEEE/Springer, covering methodology, results, discussion and future work.

Acceptance criteria
1. Demonstrated PDP reduction relative to the attached IEEE design.
2. Simulation results reproducible from the supplied decks.
3. Report written in clear academic English and ready for submission formatting.

No layout or DRC/LVS is required—focus stays on schematic-level innovation and solid, verifiable simulation evidence. If you have novel circuit tweaks, encoding variants, or low-power tricks suited to 90 nm, I am eager to see them incorporated.