Novel Low-Power MBE Cadence Design
Budget: ₹600 – ₹1,500 INR
I need a complete Cadence Virtuoso implementation of a Modified Booth Encoder that genuinely outperforms the conventional and PTL-based versions outlined in the IEEE paper “Low-Power, High-Speed, and Area-Efficient Multiplier Based on the PTL Logic Style.” The target process is the generic 90 nm CMOS node.
Scope and objectives
• Re-architect the MBE so it delivers demonstrably lower power consumption, shorter critical delay, a superior Power-Delay Product, and tangible savings in both area and overall transistor count.
• Stay faithful to the arithmetic correctness of the classic Booth algorithm while introducing novel circuit-level optimisations that justify publication-grade results.
Required work products
1. Schematic: a clean, hierarchy-organised Virtuoso schematic for the new MBE as well as baseline conventional and PTL reference versions.
2. Simulation environment: ADE-XL / Spectre testbenches that sweep PVT corners, toggle frequencies, and realistic load caps to capture power, delay, and PDP.
3. Verification: annotated timing and power waveforms proving functional correctness; include vector files and any calculator expressions used.
4. Comparative analysis: neatly formatted tables and graphs contrasting the three architectures on power, delay, PDP, area, and device count. Clearly mark the percentage gains achieved.
5. Design rationale: a short write-up (suitable for a journal appendix) explaining the transistor-level tricks, logic restructuring, or sizing strategies that led to the improvements.
Acceptance criteria
• At least 15 % reduction in PDP versus the PTL design under identical testbench conditions.
• No loss of functional coverage across all Booth recoding cases (-4 to +4).
• DRC/LVS-clean schematics suitable for later layout work.
Tool stack
Cadence Virtuoso, Spectre, ADE-XL (or ADEXL), with standard 90 nm PDK libraries.
I will provide the full IEEE reference paper, baseline schematics if needed, and report templates for the tables. Please build on that foundation and return publication-ready data and collateral.
Scope and objectives
• Re-architect the MBE so it delivers demonstrably lower power consumption, shorter critical delay, a superior Power-Delay Product, and tangible savings in both area and overall transistor count.
• Stay faithful to the arithmetic correctness of the classic Booth algorithm while introducing novel circuit-level optimisations that justify publication-grade results.
Required work products
1. Schematic: a clean, hierarchy-organised Virtuoso schematic for the new MBE as well as baseline conventional and PTL reference versions.
2. Simulation environment: ADE-XL / Spectre testbenches that sweep PVT corners, toggle frequencies, and realistic load caps to capture power, delay, and PDP.
3. Verification: annotated timing and power waveforms proving functional correctness; include vector files and any calculator expressions used.
4. Comparative analysis: neatly formatted tables and graphs contrasting the three architectures on power, delay, PDP, area, and device count. Clearly mark the percentage gains achieved.
5. Design rationale: a short write-up (suitable for a journal appendix) explaining the transistor-level tricks, logic restructuring, or sizing strategies that led to the improvements.
Acceptance criteria
• At least 15 % reduction in PDP versus the PTL design under identical testbench conditions.
• No loss of functional coverage across all Booth recoding cases (-4 to +4).
• DRC/LVS-clean schematics suitable for later layout work.
Tool stack
Cadence Virtuoso, Spectre, ADE-XL (or ADEXL), with standard 90 nm PDK libraries.
I will provide the full IEEE reference paper, baseline schematics if needed, and report templates for the tables. Please build on that foundation and return publication-ready data and collateral.