Low-Power 8-Bit Multiplier Design using PTL

This project focuses on the design and implementation of a low-power, high-speed, and area-efficient 8-bit signed multiplier using Pass Transistor Logic (PTL) for improved VLSI performance. The goal is to develop an optimized multiplier architecture by integrating PTL-based components such as XOR gates, Half Adders (HA), Full Adders (FA), and a modified Full Adder (FAINV), along with key building blocks like Modified Booth Encoding (MBE), an adder tree, and a Ripple Carry Adder (RCA). The freelancer will be responsible for designing the complete circuit, performing simulations, and validating the design using a 28nm technology node under varying voltage and frequency conditions. The project also involves layout design, performance analysis, and comparison with conventional CMOS and synthesized multipliers in terms of power consumption, delay, area, and Power-Delay Product (PDP). The main challenge lies in balancing PTL advantages such as reduced transistor count and lower power with issues like increased delay and weaker signal driving capability. The final deliverables should include schematics, simulation results, layout files, and a detailed report demonstrating measurable improvements and alignment with the results presented in the reference research paper.