6-Layer KiCad PCB Layout — LTO Battery Balancer 20A (Production-Ready for JLCPCB)
Budget: $250 – $750 AUD
OVERVIEW
--------
I need a KiCad PCB designer to take a fully verified analogue circuit design
and implement it correctly in KiCad, producing production-ready gerbers for
JLCPCB. The circuit design is complete — this is a layout and EDA
implementation job, not a design-from-scratch job.
The board is a 6-cell LTO battery active balancer, 20A per channel, entirely
analogue (no microcontroller). I need 4 identical boards to cover a 24S
15P Yinlong 66160 45Ah home battery pack. I plan to order 50 boards after
a 5-board prototype run.
BOARD SPECIFICATIONS
--------------------
Board size: 250 x 120 mm
Layers: 6 (JLCPCB stackup JLC06161H-3313)
Outer copper: 2oz (L1 F.Cu and L6 B.Cu)
Inner copper: 0.5oz (L2 through L5)
Surface finish: HASL lead-free
Soldermask: Green / White silkscreen
Manufacturer: JLCPCB — files must pass JLCPCB online DRC
Components: ~60 THT + ~25 SMD per board
Max current: 20A per channel, 3 channels per board
EDA tool required: KiCad 7 or 8 (not Altium, not EasyEDA)
WHY THE EXISTING FILES CANNOT BE USED
--------------------------------------
I have reference gerbers and documentation but they were generated
programmatically (not through an EDA tool) and have two critical defects
that would destroy the boards on first power-on:
1. CRITICAL — L6 copper fill shorts all power zones to GND.
The back copper layer has a full-board GND fill AND 6 isolated power
zones. In Gerber format all copper regions are additive, so every power
zone is shorted to GND. A proper KiCad zone fill with correct priority
settings fixes this automatically.
2. CRITICAL — Inner GND planes (L2, L4) have no anti-pads.
Solid copper fills with zero clearance around non-GND through-hole pads
means every VCC pin, inductor pad, and signal pin is shorted to GND on
those layers. KiCad generates anti-pads automatically when the design is
built correctly with proper net assignments.
Both issues are standard KiCad zone management — they only require
an experienced KiCad user who has done multi-layer boards before.
Two additional issues to fix:
3. The KiCad source files I have are documentation stubs only and cannot
be opened in KiCad. A real KiCad project must be built from scratch
using my reference gerbers and component list.
4. The L6 power zone stems at the J1 connector row are 3.8mm wide —
these should be widened to 5mm for manufacturing tolerance.
SCOPE OF WORK
-------------
1. Build a real KiCad schematic from the provided component list and
reference stub. All components, values, and connections are specified.
No circuit design decisions are required.
2. Build the 6-layer KiCad PCB with the correct JLCPCB stackup. Component
positions must match the reference gerbers exactly — this is a
constrained layout, not free placement.
3. Route all signal traces to match the reference:
- L1: 8mm wide power bus, 0.5mm signal traces, 3mm fuse bridges
- L3: 0.8mm sense traces (FU input to LM393 comparator inputs)
- L5: 0.5mm sense traces (FU output to J1 connector)
4. Create the 6 L-shaped copper pour zones on L6 (the most critical task).
Each zone connects one J1 screw terminal pad to the corresponding MOSFET
drain pad through the PCB, replacing external fly-lead wires. Zones must
use correct KiCad zone priority so the GND fill sits around them without
shorting. Full zone coordinates are provided in the documentation.
5. Verify inner GND planes (L2, L4) have correct anti-pads around all
non-GND pads. KiCad handles this automatically with correct net
assignments — just needs to be confirmed in the copper preview.
6. Run JLCPCB DRC in KiCad — zero errors required.
7. Generate the complete JLCPCB gerber package (12 gerber files + 2 drill
files) and do a test upload to JLCPCB Gerber Viewer. Provide a
screenshot of the accepted result.
8. Deliver the full native KiCad project (.kicad_pro, .kicad_sch,
.kicad_pcb, all footprint libraries). Must open cleanly in KiCad 8.
WHAT I PROVIDE
--------------
Upon project award (after NDA) I will share a ZIP containing:
- Reference gerbers for all 6 layers (exact pad coordinates, trace routes,
and zone geometry to replicate in KiCad)
- KiCad stub files (component list and topology reference)
- Verified BOM and CPL files with JLCPCB LCSC part codes and XY positions
- 9-page full-colour layer render PDF showing every layer in detail
- 78/78 verification report confirming all signal connections correct
(use this as your netlist acceptance checklist)
- A3 top-down PCB render at 1:1 scale with all component positions labelled
- Full assembly guide with component positions and designators
- JLCPCB order settings and stackup specification
L6 POWER ZONE DETAILS
----------------------
This is the key technical feature of the design. There are 6 isolated
copper zones on L6 (bottom copper), each connecting one J1 screw terminal
to one MOSFET drain pad. Zone shape: a 5mm-wide horizontal corridor at the
drain's Y position, plus a vertical stem connecting to the J1 pad row at
y=60mm. All drain pads are at x=170mm. J1 pads are at x=58 to 84mm.
Zone assignments (all at x=50 to 175mm):
Net C0- J1-P1 (x=58.00mm) -> drain y=80mm, corridor y=77.5-82.5mm
Net C1 J1-P2 (x=63.08mm) -> drain y=100mm, corridor y=97.5-102.5mm
Net C2 J1-P3 (x=68.16mm) -> drain y=40mm, corridor y=37.5-42.5mm
Net C3 J1-P4 (x=73.24mm) -> drain y=52mm, corridor y=49.5-54.5mm
Net C4 J1-P5 (x=78.32mm) -> drain y=25mm, corridor y=22.5-27.5mm
Net C5 J1-P6 (x=83.40mm) -> drain y=15mm, corridor y=12.5-17.5mm
Each zone is 5mm wide = 20.6A capacity (IPC-2221A, 2oz outer, dT=30C).
Minimum clearance between zones: 5mm. The GND fill on L6 must be lower
priority and must not touch the zone copper.
ACCEPTANCE CRITERIA
-------------------
Payment will be released when all of the following are confirmed:
1. KiCad DRC shows zero errors (include DRC report in delivery)
2. JLCPCB Gerber Viewer accepts all 12 files (include screenshot)
3. L6 zones are visibly isolated from GND fill in KiCad copper preview
4. Anti-pads present on L2 and L4 around all non-GND pads
5. All 78 verified signal connections present (checked against my report)
6. KiCad project files open cleanly in KiCad 8 on my machine
7. Pad positions within 0.1mm of reference gerber coordinates
8. JLCPCB stackup correctly set as JLC06161H-3313
Milestone payments: 50% on KiCad DRC pass, 50% on JLCPCB acceptance.
I will complete my review within 3 business days of receiving files.
REQUIREMENTS FOR BIDDERS
------------------------
- KiCad 7 or 8 must be your primary tool (not Altium or EasyEDA)
- You must have completed at least one 6-layer KiCad board before
- You must understand copper pour zone priority and inner-layer anti-pads
- JLCPCB experience required — you must know their DRC rules
- In your bid, briefly describe a multi-layer KiCad project you have
completed and provide a portfolio link or GitHub if available
- Timeline: 7 days from project award
- A simple NDA will be signed before reference files are shared
This is a 1-2 day job for an experienced KiCad user. The circuit design is
done and all trace routes, component positions, and zone geometry are fully
documented. The only genuine complexity is correctly managing the KiCad zone
fills — something any 6-layer KiCad designer will be familiar with.
--------
I need a KiCad PCB designer to take a fully verified analogue circuit design
and implement it correctly in KiCad, producing production-ready gerbers for
JLCPCB. The circuit design is complete — this is a layout and EDA
implementation job, not a design-from-scratch job.
The board is a 6-cell LTO battery active balancer, 20A per channel, entirely
analogue (no microcontroller). I need 4 identical boards to cover a 24S
15P Yinlong 66160 45Ah home battery pack. I plan to order 50 boards after
a 5-board prototype run.
BOARD SPECIFICATIONS
--------------------
Board size: 250 x 120 mm
Layers: 6 (JLCPCB stackup JLC06161H-3313)
Outer copper: 2oz (L1 F.Cu and L6 B.Cu)
Inner copper: 0.5oz (L2 through L5)
Surface finish: HASL lead-free
Soldermask: Green / White silkscreen
Manufacturer: JLCPCB — files must pass JLCPCB online DRC
Components: ~60 THT + ~25 SMD per board
Max current: 20A per channel, 3 channels per board
EDA tool required: KiCad 7 or 8 (not Altium, not EasyEDA)
WHY THE EXISTING FILES CANNOT BE USED
--------------------------------------
I have reference gerbers and documentation but they were generated
programmatically (not through an EDA tool) and have two critical defects
that would destroy the boards on first power-on:
1. CRITICAL — L6 copper fill shorts all power zones to GND.
The back copper layer has a full-board GND fill AND 6 isolated power
zones. In Gerber format all copper regions are additive, so every power
zone is shorted to GND. A proper KiCad zone fill with correct priority
settings fixes this automatically.
2. CRITICAL — Inner GND planes (L2, L4) have no anti-pads.
Solid copper fills with zero clearance around non-GND through-hole pads
means every VCC pin, inductor pad, and signal pin is shorted to GND on
those layers. KiCad generates anti-pads automatically when the design is
built correctly with proper net assignments.
Both issues are standard KiCad zone management — they only require
an experienced KiCad user who has done multi-layer boards before.
Two additional issues to fix:
3. The KiCad source files I have are documentation stubs only and cannot
be opened in KiCad. A real KiCad project must be built from scratch
using my reference gerbers and component list.
4. The L6 power zone stems at the J1 connector row are 3.8mm wide —
these should be widened to 5mm for manufacturing tolerance.
SCOPE OF WORK
-------------
1. Build a real KiCad schematic from the provided component list and
reference stub. All components, values, and connections are specified.
No circuit design decisions are required.
2. Build the 6-layer KiCad PCB with the correct JLCPCB stackup. Component
positions must match the reference gerbers exactly — this is a
constrained layout, not free placement.
3. Route all signal traces to match the reference:
- L1: 8mm wide power bus, 0.5mm signal traces, 3mm fuse bridges
- L3: 0.8mm sense traces (FU input to LM393 comparator inputs)
- L5: 0.5mm sense traces (FU output to J1 connector)
4. Create the 6 L-shaped copper pour zones on L6 (the most critical task).
Each zone connects one J1 screw terminal pad to the corresponding MOSFET
drain pad through the PCB, replacing external fly-lead wires. Zones must
use correct KiCad zone priority so the GND fill sits around them without
shorting. Full zone coordinates are provided in the documentation.
5. Verify inner GND planes (L2, L4) have correct anti-pads around all
non-GND pads. KiCad handles this automatically with correct net
assignments — just needs to be confirmed in the copper preview.
6. Run JLCPCB DRC in KiCad — zero errors required.
7. Generate the complete JLCPCB gerber package (12 gerber files + 2 drill
files) and do a test upload to JLCPCB Gerber Viewer. Provide a
screenshot of the accepted result.
8. Deliver the full native KiCad project (.kicad_pro, .kicad_sch,
.kicad_pcb, all footprint libraries). Must open cleanly in KiCad 8.
WHAT I PROVIDE
--------------
Upon project award (after NDA) I will share a ZIP containing:
- Reference gerbers for all 6 layers (exact pad coordinates, trace routes,
and zone geometry to replicate in KiCad)
- KiCad stub files (component list and topology reference)
- Verified BOM and CPL files with JLCPCB LCSC part codes and XY positions
- 9-page full-colour layer render PDF showing every layer in detail
- 78/78 verification report confirming all signal connections correct
(use this as your netlist acceptance checklist)
- A3 top-down PCB render at 1:1 scale with all component positions labelled
- Full assembly guide with component positions and designators
- JLCPCB order settings and stackup specification
L6 POWER ZONE DETAILS
----------------------
This is the key technical feature of the design. There are 6 isolated
copper zones on L6 (bottom copper), each connecting one J1 screw terminal
to one MOSFET drain pad. Zone shape: a 5mm-wide horizontal corridor at the
drain's Y position, plus a vertical stem connecting to the J1 pad row at
y=60mm. All drain pads are at x=170mm. J1 pads are at x=58 to 84mm.
Zone assignments (all at x=50 to 175mm):
Net C0- J1-P1 (x=58.00mm) -> drain y=80mm, corridor y=77.5-82.5mm
Net C1 J1-P2 (x=63.08mm) -> drain y=100mm, corridor y=97.5-102.5mm
Net C2 J1-P3 (x=68.16mm) -> drain y=40mm, corridor y=37.5-42.5mm
Net C3 J1-P4 (x=73.24mm) -> drain y=52mm, corridor y=49.5-54.5mm
Net C4 J1-P5 (x=78.32mm) -> drain y=25mm, corridor y=22.5-27.5mm
Net C5 J1-P6 (x=83.40mm) -> drain y=15mm, corridor y=12.5-17.5mm
Each zone is 5mm wide = 20.6A capacity (IPC-2221A, 2oz outer, dT=30C).
Minimum clearance between zones: 5mm. The GND fill on L6 must be lower
priority and must not touch the zone copper.
ACCEPTANCE CRITERIA
-------------------
Payment will be released when all of the following are confirmed:
1. KiCad DRC shows zero errors (include DRC report in delivery)
2. JLCPCB Gerber Viewer accepts all 12 files (include screenshot)
3. L6 zones are visibly isolated from GND fill in KiCad copper preview
4. Anti-pads present on L2 and L4 around all non-GND pads
5. All 78 verified signal connections present (checked against my report)
6. KiCad project files open cleanly in KiCad 8 on my machine
7. Pad positions within 0.1mm of reference gerber coordinates
8. JLCPCB stackup correctly set as JLC06161H-3313
Milestone payments: 50% on KiCad DRC pass, 50% on JLCPCB acceptance.
I will complete my review within 3 business days of receiving files.
REQUIREMENTS FOR BIDDERS
------------------------
- KiCad 7 or 8 must be your primary tool (not Altium or EasyEDA)
- You must have completed at least one 6-layer KiCad board before
- You must understand copper pour zone priority and inner-layer anti-pads
- JLCPCB experience required — you must know their DRC rules
- In your bid, briefly describe a multi-layer KiCad project you have
completed and provide a portfolio link or GitHub if available
- Timeline: 7 days from project award
- A simple NDA will be signed before reference files are shared
This is a 1-2 day job for an experienced KiCad user. The circuit design is
done and all trace routes, component positions, and zone geometry are fully
documented. The only genuine complexity is correctly managing the KiCad zone
fills — something any 6-layer KiCad designer will be familiar with.