Implementation and Novelty in Base Paper Design for IEEE Publication

I am seeking an experienced VLSI Research Engineer with expertise in Cadence Virtuoso, Spectre Simulation, CMOS Circuit Design, Low-Power VLSI, and IEEE Paper Writing. The task involves implementing the base paper design and introducing novelty to enhance the given base paper design. The goal is to achieve a novel architecture optimized for minimum Power Delay Product (PDP) while maintaining full-swing output and low leakage power. All claims must be supported by simulation results and comparison tables.

Deliverables include:
- Implementation of the base paper design using Cadence Virtuoso and Spectre Simulator
- Optimization of the proposed design with technical justification
- Cadence Virtuoso schematics
- Testbenches
- Transient analysis outputs
- Simulation results (including Monte Carlo analysis and PVT analysis)
- PDP comparison tables
- Step-by-step explanation of the proposed design optimization process from scratch
- IEEE conference paper