AD9361 + Zynq FPGA Design
Budget: $30 – $250 USD
I need to use AD9361 to receive and down-convert 1.5GHz center frequency input signal with 2.5MHz bandwidth to zero-IF 12bit I/Q output, sampled at 25MHz, send to Zynq FPGA.
Zynq FPGA, under internal ARM9 control, divide the I/Q signal by 1/2, 1/4, 1/8, or 1/6, output to AD9361, and modulate back to 1.5GHz for transmission.
A counter clocked by the 25MHz clock generates interrupt to the ARM9 every 3 seconds. ARM9 writes to a readable/writeable 32bit register, AXI4-Lite access, incrementing by 1. The lowest 2 bits are used to control the above 1/2, 1/4, 1/8, 1/16 output selection, thus the transmitted 1.5GHz signal level changes every 3 seconds.
Purpose of the project is to provide me a framework such that I can later modify for my application.
Zynq FPGA, under internal ARM9 control, divide the I/Q signal by 1/2, 1/4, 1/8, or 1/6, output to AD9361, and modulate back to 1.5GHz for transmission.
A counter clocked by the 25MHz clock generates interrupt to the ARM9 every 3 seconds. ARM9 writes to a readable/writeable 32bit register, AXI4-Lite access, incrementing by 1. The lowest 2 bits are used to control the above 1/2, 1/4, 1/8, 1/16 output selection, thus the transmitted 1.5GHz signal level changes every 3 seconds.
Purpose of the project is to provide me a framework such that I can later modify for my application.