Implement PCISM, a simulator for PIPE Implementation with simple memory hierarchy

This is an implementation project for processor simulators in C.

You will first write a standalone cache controller simulator csim and test it against a number of
memory traces. Correctness will be determined by matching the cache events generated by your simulator
against a reference. You will augment psim with csim to produce pcsim.

You will first implement a skeletal cache simulator that implements the control actions (the three-state finite-state machine cache controller) of a write-back cache with LRU replacement and write-allocate policies, for arbitrary numbers of sets, associativity values, and block sizes.

• You can assume that each cache read/write only accesses one single cache line.
• you will then implement functions to give you a fully functional cache simulator that implements both the
control and the data portions of the cache.
• You will Integrate the memory hierarchy simulator into the PIPE simulator. This should involve no more than updating the data memory routines to the corresponding cache routines and handling stalls resulting from cache misses.

I have a GitHub repo with the codebase and I will tell you the files needing to be changed.