Computer Architecture Laboratory

Suppose we want to add support for a new instruction to RISC-V pipelined data path.
The new instruction is the unconditional branch and link (ubl) instruction. It is an Rtype instruction that has an opcode of decimal 9 or (1001)2 and it operates as the
following:
ubl rd, rs1, rs2
R[rd]  PC + 1;
PC  R[rs1] + R[rs2];
The R-type format instruction has the following fields:
15
14..12
11..9
8..7
6..4
3..0
Funct7
rs2
rs1
Funct3
rd
opcode
R-type
Note that Funct3 and Funct7 fields are not used and should be set to zeros.
Modify the pipelined data path to allow the correct execution of the ubl instruction in
addition to the existing instructions. The branch address is determined in the
instruction decode (ID) stage. Use the Quartus block editor tools to highlight your
modification on the block/schematic diagram.
Testing and Simulation
Given the following RISC-V assembly program. Note that the code does not have
any data hazards.
Complete the following steps to test and simulate your design:
1. Encode the instructions in the given program and create the memory initialization
file to initialize your instruction memory. Show the RISC-V code (address and
instruction), encoding and results in a form of a table.
2. Create a vector waveform file (final.vwf) and insert all necessary input and
output pins to test your design (clock, PC, instruction opcodes in all stages and
registers). Make sure to show the exact number of cycles needed to execute
the above code.