Expert VHDL/Verilog Developer for 32-bit MIPS CPU with Flopoco FPU, Pipeline, and Cache
Budget: $10 – $30 USD
I am seeking a highly skilled hardware design engineer for a fixed-term academic project. The objective is to design, implement, and verify a complex 32-bit MIPS general-purpose CPU. The project will be developed using VHDL or Verilog on the EDA Playground online simulation environment.
This project is divided into two main phases with two distinct deadlines. The freelancer must be capable of handling complex processor architecture, including floating-point unit integration, pipelining, and cache memory design.
Phase 1: 32-bit MIPS Processor with Custom FPU (Deadline: 17/11)
This phase involves building the core single-cycle processor and integrating a custom floating-point unit (FPU).
Step 1.1: Base 32-bit MIPS Design
Design and implement the datapath for a 32-bit MIPS processor (including PC, register file, ALU for integers, memory interfaces, etc.).
Design and implement the main Control Unit for standard MIPS instructions.
Step 1.2: Custom ISA Definition
Define a customized/extended Instruction Set Architecture (ISA) that includes new instructions for 32-bit floating-point arithmetic.
Step 1.3: FPU Generation (Flopoco)
Use the Flopoco project to generate the VHDL/Verilog code for a 32-bit Floating Point Arithmetic Logic Unit (ULA).
Step 1.4: FPU Integration
Integrate the generated Flopoco FPU into the MIPS datapath.
Extend the Control Unit and datapath to correctly decode and execute the new floating-point instructions defined in Step 1.2. This involves managing data paths to and from the FPU.
Step 1.5: Phase 1 Verification
Create a testbench for the EDA Playground platform to verify the functionality of both standard MIPS instructions and the new floating-point instructions.
Phase 2: Pipeline & Cache Implementation (Deadline: 11/12)
This phase focuses on upgrading the performance of the Phase 1 processor by transforming it into a pipelined system with a cache.
Step 2.1: Pipeline Transformation
Convert the single-cycle design from Phase 1 into a 5-stage MIPS pipeline.
This includes implementing pipeline registers between stages.
Step 2.2: Hazard and Forwarding Logic
Implement all necessary logic for hazard detection (structural, data, and control hazards).
Implement forwarding (bypassing) units to resolve data hazards.
Implement branch logic (e.g., branch prediction or flushing) to handle control hazards.
Step 2.3: Cache Memory Design
Design and implement a Cache memory subsystem.
The specific architecture (e.g., direct-mapped, N-way set associative, write-through, write-back) is open for discussion but must be "coherent with the general project" and justified.
Step 2.4: Cache Integration
Integrate the designed Cache between the pipelined processor and the main memory.
Step 2.5: Phase 2 Verification
Update all testbenches to verify the correct operation of the pipelined processor, including its hazard-handling logic and the new cache memory.
Mandatory Deliverables (Required by Project Guidelines)
You must deliver two main items:
Compressed Code Archive: A .zip file containing all source code (.hdl or .v) and all necessary testbench files. The project must be fully replicable and runnable on the EDA Playground platform.
MIPS Assembly Test Program: A single, comprehensive MIPS Assembly program.
Functionality: This program must be designed to thoroughly "exercise" all processor instructions and resources (both standard and FPU) to demonstrate correct functionality.
CRITICAL: Commenting Requirement: The assembly program must be heavily commented. The comments must allow a reviewer to "easily understand what the program is doing" and, most importantly, clearly state the "expected results (i.e., the final state of registers or memory)" after execution.
Required Skills & Experience:
Expert-level VHDL or Verilog for complex digital design.
Proven experience in CPU Architecture: Must have prior projects involving MIPS or RISC-V processor design (Datapath and Control).
Pipelining: Demonstrable experience in designing pipelined processors, including hazard detection and forwarding.
Cache Memory: Demonstrable experience in designing and implementing cache memory.
MIPS Assembly: Ability to write and debug MIPS assembly language for verification.
EDA Playground: Familiarity with the EDA Playground environment is a strong plus.
Flopoco: Familiarity with the Flopoco project is a strong plus.
This project is divided into two main phases with two distinct deadlines. The freelancer must be capable of handling complex processor architecture, including floating-point unit integration, pipelining, and cache memory design.
Phase 1: 32-bit MIPS Processor with Custom FPU (Deadline: 17/11)
This phase involves building the core single-cycle processor and integrating a custom floating-point unit (FPU).
Step 1.1: Base 32-bit MIPS Design
Design and implement the datapath for a 32-bit MIPS processor (including PC, register file, ALU for integers, memory interfaces, etc.).
Design and implement the main Control Unit for standard MIPS instructions.
Step 1.2: Custom ISA Definition
Define a customized/extended Instruction Set Architecture (ISA) that includes new instructions for 32-bit floating-point arithmetic.
Step 1.3: FPU Generation (Flopoco)
Use the Flopoco project to generate the VHDL/Verilog code for a 32-bit Floating Point Arithmetic Logic Unit (ULA).
Step 1.4: FPU Integration
Integrate the generated Flopoco FPU into the MIPS datapath.
Extend the Control Unit and datapath to correctly decode and execute the new floating-point instructions defined in Step 1.2. This involves managing data paths to and from the FPU.
Step 1.5: Phase 1 Verification
Create a testbench for the EDA Playground platform to verify the functionality of both standard MIPS instructions and the new floating-point instructions.
Phase 2: Pipeline & Cache Implementation (Deadline: 11/12)
This phase focuses on upgrading the performance of the Phase 1 processor by transforming it into a pipelined system with a cache.
Step 2.1: Pipeline Transformation
Convert the single-cycle design from Phase 1 into a 5-stage MIPS pipeline.
This includes implementing pipeline registers between stages.
Step 2.2: Hazard and Forwarding Logic
Implement all necessary logic for hazard detection (structural, data, and control hazards).
Implement forwarding (bypassing) units to resolve data hazards.
Implement branch logic (e.g., branch prediction or flushing) to handle control hazards.
Step 2.3: Cache Memory Design
Design and implement a Cache memory subsystem.
The specific architecture (e.g., direct-mapped, N-way set associative, write-through, write-back) is open for discussion but must be "coherent with the general project" and justified.
Step 2.4: Cache Integration
Integrate the designed Cache between the pipelined processor and the main memory.
Step 2.5: Phase 2 Verification
Update all testbenches to verify the correct operation of the pipelined processor, including its hazard-handling logic and the new cache memory.
Mandatory Deliverables (Required by Project Guidelines)
You must deliver two main items:
Compressed Code Archive: A .zip file containing all source code (.hdl or .v) and all necessary testbench files. The project must be fully replicable and runnable on the EDA Playground platform.
MIPS Assembly Test Program: A single, comprehensive MIPS Assembly program.
Functionality: This program must be designed to thoroughly "exercise" all processor instructions and resources (both standard and FPU) to demonstrate correct functionality.
CRITICAL: Commenting Requirement: The assembly program must be heavily commented. The comments must allow a reviewer to "easily understand what the program is doing" and, most importantly, clearly state the "expected results (i.e., the final state of registers or memory)" after execution.
Required Skills & Experience:
Expert-level VHDL or Verilog for complex digital design.
Proven experience in CPU Architecture: Must have prior projects involving MIPS or RISC-V processor design (Datapath and Control).
Pipelining: Demonstrable experience in designing pipelined processors, including hazard detection and forwarding.
Cache Memory: Demonstrable experience in designing and implementing cache memory.
MIPS Assembly: Ability to write and debug MIPS assembly language for verification.
EDA Playground: Familiarity with the EDA Playground environment is a strong plus.
Flopoco: Familiarity with the Flopoco project is a strong plus.