PCB Design for IoT Trap Monitor
Budget: $750 – $1,500 AUD
What We're Building
A remote animal trap monitoring unit for outdoor deployment in Australia. The device sleeps on ultra-low power, wakes when a trap triggers (reed switch interrupt), acquires a GPS fix, sends an SMS alert over LTE, then returns to deep sleep. Solar-charged LiFePO4 battery. Designed for use on both standard Telstra cellular (Band 28, 700 MHz) and the new Starlink Direct-to-Cell satellite network (Band 7, 2600 MHz).
What We Need
A PCB designer to take our complete hardware specification and produce manufacturing-ready design files — schematic, layout, Gerbers, and BOM. Optionally, build 3–5 prototype boards for field testing. Production runs (Phase 2) will go to a dedicated fab house.
Two-Phase Approach
**Phase 1 (this engagement):** Design files for a dev/test board, with optional prototype build (3–5 units). We're optimising for speed and low cost, not miniaturisation. Off-the-shelf dev modules (ESP32-S3 DevKit, EG800Q breakout, u-blox M10 breakout) on a carrier PCB are acceptable if it reduces cost and lead time.
**Phase 2 (future engagement):** Fully integrated custom PCB with proper RF layout, antenna matching, size optimisation, and DFM review. Quantity: 50–100 units. Production fabrication will be handled by a dedicated fab house (JLCPCB/PCBWAY). This engagement follows successful Phase 1 field testing.
Key Components
- **MCU:** ESP32-S3-WROOM-1-N8 (3.3V, native USB-C, deep sleep ~10µA)
- **LTE Modem:** Quectel EG800Q-EU (CAT-1bis, 1.8V logic, NO integrated GNSS)
- **GPS:** u-blox MAX-M10S (standalone, NMEA 9600 baud, 3.3V logic)
- **RTC:** DS3231SN with CR2032 backup
- **Power:** 2S LiFePO4 (6.4V) → HT7333-A 3.3V LDO (MCU/GPS) + AP63300WU-7 3.8V 3A buck (modem)
- **Solar:** CN3767 MPPT buck charger from 12V panel
- **Level translation:** 3.3V ↔ 1.8V on 4 modem lines (TXB0104 or BSS138 discrete)
- **Connectors:** USB-C, nano-SIM, 2× u.FL (cellular + GNSS), JST-PH (battery, solar, reed switch), 4× expansion headers (DNP)
Critical Constraint — Firmware Compatibility
The firmware is already written and compiled against specific GPIO pin assignments ideally we avoid having to rewite this, but if you forsee obvious issues and we need to make a change that is preferable. **The same firmware binary must run on both Phase 1 and Phase 2 boards without modification.** All GPIO assignments, UART configs, power rail voltages, and logic levels must match our specification exactly. We will provide a complete pin map and the firmware `config.h` file.
What We Provide
- Complete PCB design specification (schematic netlist, circuit descriptions, layout constraints)
- Detailed design brief (requirements, power architecture, critical design notes)
- Bill of Materials with LCSC part numbers
- Firmware `config.h` (authoritative GPIO pin assignments)
- Hardware design brief (component overview, mechanical notes)
Deliverables (Phase 1)
**Design files (required):**
1. Schematic (PDF + editable source — EasyEDA, KiCad, or Altium)
2. PCB layout (editable source)
3. Gerber files (RS-274X) — ready for submission to JLCPCB/PCBWAY
4. BOM in JLCPCB/PCBWAY assembly format
5. Pick-and-place / centroid file (for PCBA)
6. 3D render (top + bottom views)
7. Design review notes — any changes, questions, or recommendations
8. Confirmation that GPIO pin map matches `config.h` exactly
**Prototype build (optional — please quote separately):**
9. 3–5 assembled prototype boards
10. Basic functional test (power-on, modem registration, GPS fix, deep sleep current, trigger wake)
Production fabrication (Phase 2, 50–100 units) will be handled by a dedicated fab house — not part of this engagement.
Skills Required
- PCB schematic capture and layout (EasyEDA, KiCad, or Altium)
- Experience with ESP32 designs
- Experience with cellular modem integration (Quectel or similar)
- Understanding of RF antenna routing (50Ω controlled impedance)
- Power supply design (LDO + buck converter)
- Level translation (3.3V ↔ 1.8V)
- Low-power / battery-operated IoT design
- Familiarity with JLCPCB or PCBWAY assembly
Nice to Have
- Experience with Quectel EG800Q or similar CAT-1bis modems and their application to australian networks, specifically the starlink D2C
- Experience with u-blox GNSS modules
- Experience with solar charge controllers (CN3767 or similar)
Budget
Please quote separately for:
1. **Design files** — schematic, layout, Gerbers, BOM (required)
2. **Prototype build** — 3–5 assembled boards + basic test (optional)
We need boards in hand as soon as practical. Phase 1 is not a complex design — the spec is complete and the BOM is ready. We're looking for someone who can move quickly.
A remote animal trap monitoring unit for outdoor deployment in Australia. The device sleeps on ultra-low power, wakes when a trap triggers (reed switch interrupt), acquires a GPS fix, sends an SMS alert over LTE, then returns to deep sleep. Solar-charged LiFePO4 battery. Designed for use on both standard Telstra cellular (Band 28, 700 MHz) and the new Starlink Direct-to-Cell satellite network (Band 7, 2600 MHz).
What We Need
A PCB designer to take our complete hardware specification and produce manufacturing-ready design files — schematic, layout, Gerbers, and BOM. Optionally, build 3–5 prototype boards for field testing. Production runs (Phase 2) will go to a dedicated fab house.
Two-Phase Approach
**Phase 1 (this engagement):** Design files for a dev/test board, with optional prototype build (3–5 units). We're optimising for speed and low cost, not miniaturisation. Off-the-shelf dev modules (ESP32-S3 DevKit, EG800Q breakout, u-blox M10 breakout) on a carrier PCB are acceptable if it reduces cost and lead time.
**Phase 2 (future engagement):** Fully integrated custom PCB with proper RF layout, antenna matching, size optimisation, and DFM review. Quantity: 50–100 units. Production fabrication will be handled by a dedicated fab house (JLCPCB/PCBWAY). This engagement follows successful Phase 1 field testing.
Key Components
- **MCU:** ESP32-S3-WROOM-1-N8 (3.3V, native USB-C, deep sleep ~10µA)
- **LTE Modem:** Quectel EG800Q-EU (CAT-1bis, 1.8V logic, NO integrated GNSS)
- **GPS:** u-blox MAX-M10S (standalone, NMEA 9600 baud, 3.3V logic)
- **RTC:** DS3231SN with CR2032 backup
- **Power:** 2S LiFePO4 (6.4V) → HT7333-A 3.3V LDO (MCU/GPS) + AP63300WU-7 3.8V 3A buck (modem)
- **Solar:** CN3767 MPPT buck charger from 12V panel
- **Level translation:** 3.3V ↔ 1.8V on 4 modem lines (TXB0104 or BSS138 discrete)
- **Connectors:** USB-C, nano-SIM, 2× u.FL (cellular + GNSS), JST-PH (battery, solar, reed switch), 4× expansion headers (DNP)
Critical Constraint — Firmware Compatibility
The firmware is already written and compiled against specific GPIO pin assignments ideally we avoid having to rewite this, but if you forsee obvious issues and we need to make a change that is preferable. **The same firmware binary must run on both Phase 1 and Phase 2 boards without modification.** All GPIO assignments, UART configs, power rail voltages, and logic levels must match our specification exactly. We will provide a complete pin map and the firmware `config.h` file.
What We Provide
- Complete PCB design specification (schematic netlist, circuit descriptions, layout constraints)
- Detailed design brief (requirements, power architecture, critical design notes)
- Bill of Materials with LCSC part numbers
- Firmware `config.h` (authoritative GPIO pin assignments)
- Hardware design brief (component overview, mechanical notes)
Deliverables (Phase 1)
**Design files (required):**
1. Schematic (PDF + editable source — EasyEDA, KiCad, or Altium)
2. PCB layout (editable source)
3. Gerber files (RS-274X) — ready for submission to JLCPCB/PCBWAY
4. BOM in JLCPCB/PCBWAY assembly format
5. Pick-and-place / centroid file (for PCBA)
6. 3D render (top + bottom views)
7. Design review notes — any changes, questions, or recommendations
8. Confirmation that GPIO pin map matches `config.h` exactly
**Prototype build (optional — please quote separately):**
9. 3–5 assembled prototype boards
10. Basic functional test (power-on, modem registration, GPS fix, deep sleep current, trigger wake)
Production fabrication (Phase 2, 50–100 units) will be handled by a dedicated fab house — not part of this engagement.
Skills Required
- PCB schematic capture and layout (EasyEDA, KiCad, or Altium)
- Experience with ESP32 designs
- Experience with cellular modem integration (Quectel or similar)
- Understanding of RF antenna routing (50Ω controlled impedance)
- Power supply design (LDO + buck converter)
- Level translation (3.3V ↔ 1.8V)
- Low-power / battery-operated IoT design
- Familiarity with JLCPCB or PCBWAY assembly
Nice to Have
- Experience with Quectel EG800Q or similar CAT-1bis modems and their application to australian networks, specifically the starlink D2C
- Experience with u-blox GNSS modules
- Experience with solar charge controllers (CN3767 or similar)
Budget
Please quote separately for:
1. **Design files** — schematic, layout, Gerbers, BOM (required)
2. **Prototype build** — 3–5 assembled boards + basic test (optional)
We need boards in hand as soon as practical. Phase 1 is not a complex design — the spec is complete and the BOM is ready. We're looking for someone who can move quickly.