LC Resonator Frequency Control Subsystem
Budget: £20 – £250 GBP
[This AI generated description is only partially accurate. A more accurate one will be provided]
I have two separate LC tanks that must run in lock-step at around 50kHz. The goal is to keep their resonant frequencies matched to within roughly ±20 Hz while they drift with temperature, load, and component ageing.
What I already have:
• The basic LC topologies for each resonator.
• Direct access points for sensing voltage or current in each tank.
• A rough block-diagram concept that suggests using either an analogue phase detector with a varactor tuner or a small MCU driving a DDS/PLL loop, but I am open to better ideas.
What I need from you:
1. A concrete circuit-level design that continually measures the two tanks and adjusts one (or both) so their peaks coincide within the stated tolerance.
2. Component selection that can be purchased today; please avoid exotic parts unless absolutely essential.
3. A brief design report (PDF) summarising theory of operation, key calculations, and test results.
4. Optional but welcome: a small two-layer PCB layout in EasyEDA showing how you would implement the control section.
Acceptance criteria
• Closed-loop accuracy proven inside ±20 Hz around the 50kHz frequency.
• Lock recovery within 100 ms after a deliberate 1 % frequency step.
• All design files handed over in editable form.
If you have experience with low-frequency PLLs, varactor tuning, or microcontroller-based auto-tuning loops, this should be a straightforward but satisfying project. Feel free to suggest alternative architectures if they hit the same performance marks.
I have two separate LC tanks that must run in lock-step at around 50kHz. The goal is to keep their resonant frequencies matched to within roughly ±20 Hz while they drift with temperature, load, and component ageing.
What I already have:
• The basic LC topologies for each resonator.
• Direct access points for sensing voltage or current in each tank.
• A rough block-diagram concept that suggests using either an analogue phase detector with a varactor tuner or a small MCU driving a DDS/PLL loop, but I am open to better ideas.
What I need from you:
1. A concrete circuit-level design that continually measures the two tanks and adjusts one (or both) so their peaks coincide within the stated tolerance.
2. Component selection that can be purchased today; please avoid exotic parts unless absolutely essential.
3. A brief design report (PDF) summarising theory of operation, key calculations, and test results.
4. Optional but welcome: a small two-layer PCB layout in EasyEDA showing how you would implement the control section.
Acceptance criteria
• Closed-loop accuracy proven inside ±20 Hz around the 50kHz frequency.
• Lock recovery within 100 ms after a deliberate 1 % frequency step.
• All design files handed over in editable form.
If you have experience with low-frequency PLLs, varactor tuning, or microcontroller-based auto-tuning loops, this should be a straightforward but satisfying project. Feel free to suggest alternative architectures if they hit the same performance marks.