Complex High-Speed PCB Layout
Budget: $10 – $30 USD
The full schematic for my MYC-LD25X “Hat” board is locked down; what remains is a rigorous placement and routing job in Altium Designer. The design is feature-dense—dual Gigabit Ethernet (RTL8211F-CG, RGMII), USB 3.0 Type-C with STUSB1600 and FUSB340, a USB2514B hub, LVDS/DSI/CSI lanes, an ES8388 codec, plus SDIO and robust power conditioning—so signal integrity, impedance control, and EMI/EMC best practices must guide every trace.
The board must fit a custom outline (I’ll supply the STEP/DXF drawing) that mates with a standard Raspberry Pi header stack-up while honoring keep-outs for an enclosure. High-speed pairs need length-tuning, differential spacing, and reference-plane continuity; the layout also has to respect 90 Ω USB 3.0 and 50 Ω single-ended constraints. All routing layers, via types, and copper pours should align with a 4-layer stack I will share, though I’m open to your recommendations if additional layers materially improve performance.
Deliverables
• Altium Designer project folder with tidy, documented layer stack and rules
• Fabrication outputs and assembly drawings
• Length-matching / impedance report and DRC checklist showing zero violations
• Brief design note highlighting any critical layout decisions or trade-offs
I’ll provide the complete schematic, BOM, mechanical outline, and preliminary stack-up the moment we start. If you have recent examples of similarly complex, high-speed boards routed in Altium, that will help me gauge fit quickly.
The price will be discussed.
The board must fit a custom outline (I’ll supply the STEP/DXF drawing) that mates with a standard Raspberry Pi header stack-up while honoring keep-outs for an enclosure. High-speed pairs need length-tuning, differential spacing, and reference-plane continuity; the layout also has to respect 90 Ω USB 3.0 and 50 Ω single-ended constraints. All routing layers, via types, and copper pours should align with a 4-layer stack I will share, though I’m open to your recommendations if additional layers materially improve performance.
Deliverables
• Altium Designer project folder with tidy, documented layer stack and rules
• Fabrication outputs and assembly drawings
• Length-matching / impedance report and DRC checklist showing zero violations
• Brief design note highlighting any critical layout decisions or trade-offs
I’ll provide the complete schematic, BOM, mechanical outline, and preliminary stack-up the moment we start. If you have recent examples of similarly complex, high-speed boards routed in Altium, that will help me gauge fit quickly.
The price will be discussed.