FPGA Developer Recruitment-Hardware Optimization Development
Budget: $250 – $750 USD
You will develop the firmware for the hardware accelerator. You will use your own hardware accelerator to develop firmware for calculating image processing in parallel. You will mainly develop in C ++, but since there is a part that uses HDL for the accelerator part, it is necessary to understand the computer architecture. The accelerator has both GPU and FPGA functions, and is a system that can dynamically connect fixed ALUs and various logic circuits. In the firmware, the processing from building the wiring to the accelerator and writing the calculation result to the memory of the CPU is implemented as a C ++ function according to the processing requested by the CPU.