Altium PCB Layout for Xilinx Zynq with DDR Ram project
Budget: £750 – £1,500 GBP
I am updating the design of a FPGA board and would like to out source the layout phase. The board consists of the following key components:
• FPGA - Xilinx zynq 400 ball device
• RAM DDR3
• Ethernet
• I2C 8 I2C slaves on two I2C ports
• SPI interfaces to 4 SPI interfaces
The design requires a flexi rigid PCB and I anticipate that the FPGA section will require 6 layers though the time critical nets will need to be located on the outer most layers. I am looking for a designer who will collaborate on finalising the schematics and will complete the PCB layout based on PBC manufacturers design tolerances and rules. There are be several of groups of tracks that need their lengths matched and impedance levels maintained.
• FPGA - Xilinx zynq 400 ball device
• RAM DDR3
• Ethernet
• I2C 8 I2C slaves on two I2C ports
• SPI interfaces to 4 SPI interfaces
The design requires a flexi rigid PCB and I anticipate that the FPGA section will require 6 layers though the time critical nets will need to be located on the outer most layers. I am looking for a designer who will collaborate on finalising the schematics and will complete the PCB layout based on PBC manufacturers design tolerances and rules. There are be several of groups of tracks that need their lengths matched and impedance levels maintained.