High-speed AXI4 DMA transmit from PL to DDR4 using SG in Petalinux — 2

This project is to design a AXI4 DMA test program for the Xilinx Zynq UltraScale board to test maximum transmit speed from PL to DDR4 in PS via HP. Transmitted data from one data source port generated in PL, it is sent from PL to PS, and is saved in DDR4 as a block of … Continue reading High-speed AXI4 DMA transmit from PL to DDR4 using SG in Petalinux — 2